Field of the Invention
The present invention relates to a semiconductor memory device having a memory cell array in which a multiplicity of memory cells each including an isolation transistor and a storage capacitor are configured in a matrix-like manner between a word line and a bit line.
As is known, DRAM cells (Dynamic Random Access Memory) include a cell capacitor, on which the memory information is stored as quantity of charge, and a MOS isolation or selection transistor that either connects a terminal of the cell capacitor to the bit line or isolates the terminal of the cell capacitor from the bit line. The other terminal of the cell capacitor is at a fixed potential, the so-called plate. The MOS isolation transistors are driven via word lines.
FIG. 23 diagrammatically shows prior art DRAM memory cells Z each including an isolation transistor T and a cell capacitor C. These memory cells Z are located in a matrix-like manner in a memory cell array with word lines WL and bit lines BL. The cell capacitor C lies between a plate PL and the isolation transistor T. The gate of the isolation transistor T is driven by a word line WL and the source or drain is connected to a bit line BL.
The memory cells themselves can be realized in different ways. In the case of the so-called stacked cell, the storage capacitor lies above the MOS isolation transistor, while in the case of the trench cell, the storage capacitor is provided below the MOS isolation transistor.
With increasing miniaturization, in trench memory cells endeavors are made to incorporate the MOS isolation transistor vertically into the trench. The technological realization of such a memory cell is relatively difficult.
In all miniaturizations of stacked cells and trench cells, at least one of the following problems always arises:
(a) the reverse current of the MOS isolation transistors rises since, in particular, the channel length thereof becomes shorter; and/or
(b) the current of the MOS isolation transistors decreases.
As is known, bipolar transistors and MOS transistors differ, inter alia, in the profile of the drain current (collector current) ID in dependence on the voltage VGS or VBE present between the gate and the source or the base and the emitter, respectively. FIG. 24 shows this dependence for a MOS transistor with a threshold voltage VT=0.1 V or VT=0.4 V and for a bipolar transistor, in which the areas for the width and the length of the channel of the MOS transistors and the emitter area of the bipolar transistor are assumed to have the same magnitude. As can be seen, from this FIG. 24, the slope of the current curves for the MOS transistors is significantly shallower than in the case of the bipolar transistor.
This means then, that below a base-emitter voltage VBE of about 0.7 V, the bipolar transistor turns off significantly earlier than the MOS transistors, and the reverse currents for VBE=0 V are less than 10xe2x88x9215 A in the case of bipolar transistors with a minimal size. This is comparable with the reverse currents of MOS transistors with threshold voltages VT above 1 V.
Above a base-emitter voltage VBE=0.7 V, the current of bipolar transistors is considerably greater than in the case of MOS transistors on account of the exponential dependence on the base-emitter voltage.
To summarize, the following thus emerges:
given the same area as MOS transistors, above a specific drain voltage UD of 0.7 V, for example, bipolar transistors have a higher current than MOS transistors.
Furthermore, given the same area as MOS transistors, below a specific drain voltage UD of 0.7 V, for example, bipolar transistors have lower reverse currents than MOS transistors. This means that, given the same area, bipolar transistors conduct better than MOS transistors.
In order to solve the above-outlined problem area of the excessively high reverse currents and excessively low active currents in the case of memory configurations, it would thus be expedient, in principle, to use bipolar transistors instead of MOS transistors as isolation transistors in DRAM memory cells. However, this has been regarded as being impossible heretofore in the case of a memory cell structure in accordance with that shown in FIG. 23, since in the case of this structure, on account of the very high base voltages UBE=U(xe2x80x9c1xe2x80x9d)+0.7 V required for a xe2x80x9c1xe2x80x9d state during writing, word line currents that are much too large and that can no longer be processed result if a xe2x80x9c0xe2x80x9d state is to be written to a different cell on this word line.
It is accordingly an object of the invention to provide a semiconductor memory configuration and a DRAM configuration which overcome the above-mentioned disadvantages of the prior art apparatus of this general type.
In particular, it is an object of the invention, in a departure from the prior art, to provide a semiconductor memory configuration in which the isolation transistors have a lower reverse current in conjunction with a high active current.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor memory configuration, including: a plurality of word lines; a plurality of bit lines; and a memory cell array including a plurality of memory cells configured in a matrix between the plurality of the word lines and the plurality of the bit lines. Each one of the memory cells includes a storage capacitor and an isolation transistor formed as a bipolar transistor.
In accordance with an added feature of the invention, each one of the memory cells includes a storage node connecting the storage capacitor thereof to the isolation transistor thereof; and in each one of the memory cells, the storage capacitor thereof is connected to a respective one of the plurality of the bit lines.
In accordance with an additional feature of the invention, in each one of the memory cells, the isolation transistor thereof has: a base connected to a respective one of the plurality of the word lines, an emitter for being held at a plate potential, and a collector that is connected to the storage node thereof.
In accordance with another feature of the invention, the storage capacitor of each one the memory cells has a high-epsilon insulator.
In accordance with a further feature of the invention, the high-epsilon insulator includes BST.
In accordance with a further added feature of the invention, the bipolar transistor of each one of the memory cells is an npn transistor.
In accordance with a further additional feature of the invention, each one of the word lines is formed by a doped semiconductor region.
In accordance with an added feature of the invention, there is provided, a doped semiconductor region for feeding a plate potential therethrough.
In accordance with an additional feature of the invention, there is provided, a silicon substrate on which the memory cell array is configured.
In accordance with yet an added feature of the invention, there is provided, an additional word line.
In accordance with yet an additional feature of the invention, the additional word line includes aluminum.
In accordance with yet another feature of the invention, in each one of the memory cells, the storage capacitor thereof is formed in a trench.
In accordance with yet a further feature of the invention, the word lines are formed from siliconized material.
In accordance with yet a further added feature of the invention, the storage capacitor of each one of the memory cells has a dielectric that includes an ONO layer.
In accordance with an added feature of the invention, the bipolar transistor of each one of the memory cells is a pnp transistor configured for receiving suitable word line voltages.
In the case of a semiconductor memory configuration of the type mentioned in the introduction, this object is achieved according to the invention by virtue of the fact that the isolation transistor is a bipolar transistor. In this case, in each memory cell, the storage capacitor is connected on the one hand to the bit line and on the other hand, via a storage node, to the isolation transistor. The base of the isolation transistor is connected to the word line, the emitter of the isolation transistor is at plate potential and the collector of the isolation transistor is connected to the storage node.
The invention thus enables a completely new kind of semiconductor memory configuration in which bipolar transistors can be used as isolation transistors in the memory cell array. This yields considerable advantages:
Given the same area as MOS transistors, above a specific drain voltage UD of 0.7 V, for example, bipolar transistors have a higher current than MOS transistors.
Furthermore, given the same area as MOS transistors, below a specific drain voltage UD of 0.7 V, for example, bipolar transistors have lower reverse currents than MOS transistors. This means that, given the same area, bipolar transistors conduct and block better than MOS transistors.
Bipolar transistors have favorable geometrical configuration possibilities and have an expedient technological construction.
In inventive semiconductor memory configuration of a storage capacitor and bipolar isolation transistor, unlike in the case of the conventional DRAM structures using MOS technology, the disturbance by the word line pulse on the bit line is extremely small.
With the inventive semiconductor memory configuration of a storage capacitor and a bipolar isolation transistor, it is possible to establish very small cells having an area requirement of 4 F2 given an open structure (F=minimum dimension).
With the inventive semiconductor memory configuration of a storage capacitor and a bipolar isolation transistor, it is possible to produce symmetrical cell structures for the memory content I and the inverted content NI in a xe2x80x9cfoldedxe2x80x9d structure with an area requirement of 8 F2.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor memory device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.